Field of the Invention
Embodiments of the invention relate to an organic light emitting display and a method for driving the same.
Discussion of the Related Art
An active matrix organic light emitting display includes organic light emitting diodes (OLEDs) capable of emitting light by itself and has advantages of a fast response time, a high light emitting efficiency, a high luminance, a wide viewing angle, and the like.
The OLED serving as a self-emitting element includes an anode electrode, a cathode electrode, and an organic compound layer formed between the anode electrode and the cathode electrode. The organic compound layer includes a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL. When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the emission layer EML and form excitons. As a result, the emission layer EML generates visible light.
The organic light emitting display has an array of pixels, each including the OLED, and a luminance of the pixels can be adjusted depending on the grayscale of video data. As shown in FIG. 1, each pixel according to the related art may include a driving thin film transistor (TFT) DT controlling a driving current applied to the OLED and a switching unit SC programming a gate-source voltage (hereinafter, referred to as “Vgs”) of the driving TFT DT. The driving TFT DT generates a drain-source current (hereinafter, referred to as “Ids”) based on the programmed Vgs and supplies the Ids to the OLED as the driving current. An amount of light emitted by the OLED is determined depending on the driving current.
A high potential driving power (hereinafter, referred to as “VDDEL”) is applied to one electrode (for example, a drain electrode) of the driving TFT DT, and a low potential driving power (hereinafter, referred to as “VSSEL”) is applied to the cathode electrode of the OLED, so that the driving current can flow in each pixel.
The VDDEL according to the related art exists in a saturation region RG2 on the Vds-Ids plane of the driving TFT DT as shown in FIG. 2, so that the stability of an operation of the driving TFT DT is secured. The saturation region RG2 indicates a voltage region in which the Ids does not substantially change in spite of changes in the Vds. The saturation region RG2 may be located on the right side of a boundary point BP on the Vds-Ids plane. An active region RG1 is differentiated from the saturation region RG2 by the boundary point BP and indicates a voltage region in which the Ids changes depending on changes in the Vds. The active region RG1 may be located on the left side of the boundary point BP on the Vds-Ids plane.
The VDDEL is uniformly determined with respect to all display panels of the same model in consideration of the electrical characteristics of a display panel including a drain-source voltage (hereinafter, referred to as “Vds”) depending on the Vgs of the driving TFT DT, a line resistance of a power line, changes in an operating voltage Voled of the OLED, etc. As shown in FIG. 2, the VDDEL is determined to have a sufficient voltage margin Vmg from the boundary point BP in consideration of a process (or manufacturing) deviation of all the display panels, so that the driving TFT DT can always operate in the saturation region RG2. The boundary point BP may have a different value in each display panel due to minor deviations of the electrical characteristics. A voltage of the boundary point BP has a maximum value in the worst-performing display panel having a large characteristic deviation among the display panels of the same model and has a minimum value in the best-performing display panel not having any characteristic deviation among the display panels of the same model. The boundary point BP is characterized in that it may be shifted to the right due to the degradation of the driving TFT DT and the OLED over time.
As shown in FIG. 3, the related art determines the voltage (8V) of the boundary point BP of the worst-performing display panel (A) among the display panels of the same model as a reference voltage and adds a voltage margin Vmg1 (0.5V) to the reference voltage in consideration of changes over time, thereby determining a final VDDEL (8.5V). Then, the final VDDEL (8.5V) is applied to the best-performing display panel (B) as well as the worst-performing display panel (A). As described above, in the related art, because the VDDEL applied to the display panels of the same model is determined based on the worst-performing display panel, the voltage margin from the boundary point BP has a different value in each display panel. Namely, the voltage margin Vmg1 may be 0.5V in the worst-performing display panel (A), but the voltage margin Vmg2 may be 1.5V in the best-performing display panel (B). According to the related art, display panels having the electrical characteristics similar to the best-performing display panel have unnecessarily large voltage margins.
Such unnecessarily large voltage margin leads to an unnecessary increase in power consumption. The problem is accentuated in mobile devices and smart devices implementing the organic light emitting display. In wearable smart devices having small-capacity battery power, low power consumption is of paramount importance. Therefore, the related art method of uniformly determining the VDDEL in a non-optimal manner is not suitable to be applied to certain OLED devices such as wearable smart devices.